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FAULT-TOLERANCE TECHNIQUES FOR SPACECRAFT CONTROL COMPUTERS
Título:
FAULT-TOLERANCE TECHNIQUES FOR SPACECRAFT CONTROL COMPUTERS
Subtítulo:
Autor:
YANG, M
Editorial:
JOHN WILEY
Año de edición:
2017
Materia
INGENIERIA DE CONTROL - GENERAL
ISBN:
978-1-119-10727-9
Páginas:
344
150,00 €

 

Sinopsis

Comprehensive coverage of all aspects of space application oriented fault tolerance techniques

 Experienced expert author working on fault tolerance for Chinese space program for almost three decades
 Initiatively provides a systematic texts for the cutting-edge fault tolerance techniques in spacecraft control computer, with emphasis on practical engineering knowledge
 Presents fundamental and advanced theories and technologies in a logical and easy-to-understand manner
 Beneficial to readers inside and outside the area of space applications



Table of Contents

Brief Introduction xiii

Preface xv

1 Introduction 1

1.1 Fundamental Concepts and Principles of Fault -tolerance Techniques 1

1.1.1 Fundamental Concepts 1

1.1.2 Reliability Principles 4

1.1.2.1 Reliability Metrics 4

1.1.2.2 Reliability Model 6

1.2 The Space Environment and Its Hazards for the Spacecraft Control Computer 9

1.2.1 Introduction to Space Environment 9

1.2.1.1 Solar Radiation 9

1.2.1.2 Galactic Cosmic Rays (GCRs) 10

1.2.1.3 Van Allen Radiation Belt 10

1.2.1.4 Secondary Radiation 12

1.2.1.5 Space Surface Charging and Internal Charging 12

1.2.1.6 Summary of Radiation Environment 13

1.2.1.7 Other Space Environments 14

1.2.2 Analysis of Damage Caused by the Space Environment 14

1.2.2.1 Total Ionization Dose (TID) 14

1.2.2.2 Single Event Effect (SEE) 15

1.2.2.3 Internal/surface Charging Damage Effect 20

1.2.2.4 Displacement Damage Effect 20

1.2.2.5 Other Damage Effect 20

1.3 Development Status and Prospects of Fault Tolerance Techniques 21

References 25

2 Fault -Tolerance Architectures and Key Techniques 29

2.1 Fault - tolerance Architecture 29

2.1.1 Module -level Redundancy Structures 30

2.1.2 Backup Fault -tolerance Structures 32

2.1.2.1 Cold -backup Fault -tolerance Structures 32

2.1.2.2 Hot -backup Fault -tolerance Structures 34

2.1.3 Triple -modular Redundancy (TMR) Fault -tolerance Structures 36

2.1.4 Other Fault -tolerance Structures 40

2.2 Synchronization Techniques 40

2.2.1 Clock Synchronization System 40

2.2.1.1 Basic Concepts and Fault Modes of the Clock Synchronization System 40

2.2.1.2 Clock Synchronization Algorithm 41

2.2.2 System Synchronization Method 52

2.2.2.1 The Real -time Multi -computer System Synchronization Method 52

2.2.2.2 System Synchronization Method with Interruption 56

2.3 Fault -tolerance Design with Hardware Redundancy 60

2.3.1 Universal Logic Model and Flow in Redundancy Design 60

2.3.2 Scheme Argumentation of Redundancy 61

2.3.2.1 Determination of Redundancy Scheme 61

2.3.2.2 Rules Obeyed in the Scheme Argumentation of Redundancy 62

2.3.3 Redundancy Design and Implementation 63

2.3.3.1 Basic Requirements 63

2.3.3.2 FDMU Design 63

2.3.3.3 CSSU Design 64

2.3.3.4 IPU Design 65

2.3.3.5 Power Supply Isolation Protection 67

2.3.3.6 Testability Design 68

2.3.3.7 Others 68

2.3.4 Validation of Redundancy by Analysis 69

2.3.4.1 Hardware FMEA 69

2.3.4.2 Redundancy Switching Analysis (RSA) 69

2.3.4.3 Analysis of the Common Cause of Failure 69

2.3.4.4 Reliability Analysis and Checking of the Redundancy Power 70

2.3.4.5 Analysis of the Sneak Circuit in the Redundancy Management Circuit 72

2.3.5 Validation of Redundancy by Testing 73

2.3.5.1 Testing by Failure Injection 73

2.3.5.2 Specific Test for the Power of the Redundancy Circuit 74

2.3.5.3 Other Things to Note 74

References 74

3 Fault Detection Techniques 77

3.1 Fault Model 77

3.1.1 Fault Model Classified by Time 78

3.1.2 Fault Model Classified by Space 78

3.2 Fault Detection Techniques 80

3.2.1 Introduction 80

3.2.2 Fault Detection Methods for CPUs 81

3.2.2.1 Fault Detection Methods Used for CPUs 82

3.2.2.2 Example of CPU Fault Detection 83

3.2.3 Fault Detection Methods for Memory 87

3.2.3.1 Fault Detection Method for ROM 88

3.2.3.2 Fault Detection Methods for RAM 91

3.2.4 Fault Detection Methods for I/Os 95

References 96

4 Bus Techniques 99

4.1 Introduction to Space -borne Bus 99

4.1.1 Fundamental Concepts 99

4.1.2 Fundamental Terminologies 99

4.2 The MIL -STD -1553B Bus 100

4.2.1 Fault Model of the Bus System 101

4.2.1.1 Bus -level Faults 103

4.2.1.2 Terminal Level Faults 104

4.2.2 Redundancy Fault -tolerance Mechanism of the Bus System 106

4.2.2.1 The Bus -level Fault -tolerance Mechanism 107

4.2.2.2 The Bus Controller Fault -tolerance Mechanism 108

4.2.2.3 Fault -tolerance Mechanism of Remote Terminals 113

4.3 The CAN Bus 116

4.3.1 The Bus Protocol 117

4.3.2 Physical Layer Protocol and Fault -tolerance 117

4.3.2.1 Node Structure 117

4.3.2.2 Bus Voltage 118

4.3.2.3 Transceiver and Controller 119

4.3.2.4 Physical Fault -tolerant Features 119

4.3.3 Data Link Layer Protocol and Fault -tolerance 120

4.3.3.1 Communication Process 120

4.3.3.2 Message Sending 120

4.3.3.3 The President Mechanism of Bus Access 120

4.3.3.4 Coding 121

4.3.3.5 Data Frame 121

4.3.3.6 Error Detection 122

4.4 The SpaceWire Bus 124

4.4.1 Physical Layer Protocol and Fault -tolerance 126

4.4.1.1 Connector 126

4.4.1.2 Cable 126

4.4.1.3 Low Voltage Differential Signal 126

4.4.1.4 Data Filter (DS) Coding 128

4.4.2 Data Link Layer Protocol and Fault -tolerance 129

4.4.2.1 Packet Character 129

4.4.2.2 Packet Parity Check Strategy 131

4.4.2.3 Packet Structure 131

4.4.2.4 Communication Link Control 131

4.4.3 Networking and Routing 136

4.4.3.1 Major Technique used by the SpaceWire Network 136

4.4.3.2 SpaceWire Router 138

4.4.4 Fault -tolerance Mechanism 139

4.5 Other Buses 141

4.5.1 The IEEE 1394 Bus 141

4.5.2 Ethernet 143

4.5.3 The I2C Bus 145

References 148

5 Software Fault -Tolerance Techniques 151

5.1 Software Fault -tolerance Concepts and Principles 151

5.1.1 Software Faults 151

5.1.2 Software Fault -tolerance 152

5.1.3 Software Fault Detection and Voting 153

5.1.4 Software Fault Isolation 154

5.1.5 Software Fault Recovery 155

5.1.6 Classification of Software Fault -tolerance Techniques 156

5.2 Single -version Software Fault -tolerance Techniques 156

5.2.1 Checkpoint and Restart 157

5.2.2 Software -implemented Hardware Fault -tolerance 160

5.2.2.1 Control Flow Checking by Software Signatures (CFCSS) 161

5.2.2.2 Error Detection by Duplicated Instructions (EDDI) 164

5.2.3 Software Crash Trap 165

5.3 Multiple -version Software Fault -tolerance Techniques 165

5.3.1 Recovery Blocks (RcB) 165

5.3.2 N -version Programming (NVP) 167

5.3.3 Distributed Recovery Blocks (DRB) 168

5.3.4 N Self -checking Programming (NSCP) 169

5.3.5 Consensus Recovery Block (CRB) 172

5.3.6 Acceptance Voting (AV) 172

5.3.7 Advantage and Disadvantage of Multiple -version Software 172

5.4 Data Diversity Based Software Fault -tolerance Techniques 173