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An introduction to the fundamentals of semiconductor physics and engineering

This book discusses fundamental semiconductor physics of devices and on-chip interconnections for physicists and links these concepts to engineering applications and case studies of computer chips. The book is organized in three parts. The first part deals with the representation of information and computation. The second part covers semiconductor device physics within the context of computation. The third part reviews chip design and semiconductor fabrication. The book includes relevant equations, with the aim of closing the gap in the existing literature with actual case studies and engineering applications. Examples are provided in each chapter to illustrate physical and electrical concepts through the use of high-performance silicon technologies.

Introductory Semiconductor Device Physics for Chip Design and Manufacturing:

Provides physical descriptions and illustrations with data visualizations to facilitate intuitive understanding of semiconductor physics, devices and on-chip interconnections
Blends theoretical physics treatment with engineering applications and real case studies for manufactured chips
Presents complementary-metal-oxide-semiconductor (CMOS) transistors in high-performance server microprocessors with static CMOS combinational digital circuit design examples
Offers a rich array of student problem sets, mid-term exams, and final exams with a glossary at the end of the book
M. Y. Lanzerotti, PhD, has over 15 years of engineering experience in designing integrated circuits for high-performance server chips and aerospace applications. Dr. Lanzerotti is Assistant Professor of Physics at Augsburg College and previously held positions as Associate Professor of Computer Engineering at Air Force Institute of Technology, Instructor at Harvard Summer School, Visiting Faculty Fellow at Pacific Lutheran University, Visiting Faculty Fellow at Sapienza University of Rome, and Research Staff Member at IBM Thomas J. Watson Research Center. This book is inspired from Dr. Lanzerotti's course, "Introductory Semiconductor Device Physics for Chip Design and Manufacturing,ö at Harvard Summer School. Dr. Lanzerotti holds physics degrees from Harvard College, the University of Cambridge, and Cornell University. Dr. Lanzerotti holds four U.S. patents, was awarded an IEEE Technical Innovation Award in 2007 and an IBM Outstanding Research Contribution Award in 1998, and was Editor-in-Chief of the IEEE Solid-State Circuits Society Magazine.



Table of Contents

List of Figures xxi

List of Tables lix

Foreword lxxv

Preface lxxvii

Acknowledgments lxxix

Acronyms lxxxiii

Introduction lxxxvii

I.1 J. J. Thomson and the Discovery of the Electron lxxxviii

I.2 Notation xcii

I.3 Mathematics xcii

I.4 Electricity xciv

I.5 The Delay in a Wire is Nonzero xciv

I.6 The Delay in a Device is Nonzero xcvi

I.7 High Performance Silicon Technology xcvii

I.8 High Performance Computing (HPC) xcviii

I.9 Organization of this Book xcix

PART I REPRESENTATION OF INFORMATION AND COMPUTATION

1 Representation of Information and Computation 3

1.1 Information 4

1.2 Alan Turing, John von Neumann, and Claude Shannon 24

1.3 High Performance Silicon Technology 28

1.4 Catalog of Computation Hardware 58

2 Computation and Basic Logic Functions 81

2.1 Rules of Switching Algebra 82

2.2 Truth Tables and Basic Logic Gates 85

2.3 Combinational Gates 90

2.4 Binary Addition 103

2.5 Binary Addition with a Full Adder Cell 104

2.6 Time-Dependent Properties of Propagating Signals 107

2.7 Binary Addition with a Two-bit Adder 114

2.8 Binary Addition with a Four-bit Adder 117

2.9 Binary Addition with an N-bit Adder 122

2.10 Switching Function for the Sum S = S(A;B;C) in a One-bit Full Adder Cell 122

2.11 Switching Function for the Output Carry Bit C0 = C0 (A;B;C) in a Full Adder Cell 124

2.12 Switching Function for the Sum S = S(A;B;C;C0) in a Full Adder Cell 125

2.13 Second Example of a One-bit Binary Adder 135

2.14 Catalog of Signal Propagation 141

3 Identification of Logic Functions through the Truth Table 149

3.1 Switch Model of the Inverter 150

3.2 Switch Model of the Buffer 166

3.3 Switch Model of the NAND2 Gate 166

3.4 Switch Model of the NOR2 Gate 171

3.5 Transistor Diagram of Full Adder 174

3.6 Dynamic Power Dissipation in an Inverter 176

3.7 Dynamic Power Dissipation in an Inverter Chain 184

3.8 Catalog of Switching Probabilities 186

PART II SEMICONDUCTORS AND SEMICONDUCTOR DEVICES

4 Metal-Oxide-Semiconductor (MOS) Capacitor 247

4.1 Parallel-Plate Capacitor 248

4.2 Metal 256

4.3 Semiconductor 265

4.4 Insulator 278

4.5 Semiconductor-Insulator Interface (Si ?? SiO2) 287

4.6 The p-n Junction, n-p Junction, and Side View of MOS Physical Structure 288

4.7 Visualization of Transistor Behavior 293

4.8 Energy Band Diagram for a Metal-Oxide-Semiconductor (MOS) Structure with Vg = 0 V 294

4.9 Energy Band Diagram for a Metal-Oxide-Semiconductor (MOS) Structure with Vg > Vt 303

4.10 Catalog of Energy Band Diagram Terms and Concepts 307

4.11 Catalog of Electrical Components 313

5 Three Terminal Devices 325

5.1 Complementary Metal Oxide Semiconductor Devices (CMOS) 325

5.2 n-type Field-E_ect Transistor (nFET) 331

5.3 p-type Field-E_ect Transistor (pFET) 341

5.4 Dependence of Inverter Delay on Metal-Oxide-Semiconductor (MOS) Structure, Electron Mobility, and Hole Mobility 342

5.5 Voltage Transfer Curve (VTC) for Input VoltageWaveform and Output Voltage Waveform at an Inverter 348

5.6 Dependence of Inverter Rise time and Inverter Fall time on Metal-Oxide-Semiconductor (MOS) Structure, Electron Mobility, and Hole Mobility 353

6 Miniaturization of Field-E_ect Transistors 355

6.1 Gordon Moore´s Law 356

6.2 Robert Dennard´s Scaling Rules 361

6.3 Technology Projections of the International Technology Roadmap for Semiconductors (ITRS) 372

PART III SEMICONDUCTOR DESIGN AND MANUFACTURING

7 On-chip Interconnections 379

7.1 Introduction 380

7.2 Pi Models for Interconnect 406

7.3 Branching: Star Wiring Configuration 417

7.4 Effective Materials Properties of Interconnections 430

7.5 Back-End-of-Line BEOL Interconnection Architectures 462

7.6 Catalog of Hierarchical Back-End-of-Line (BEOL) Interconnection Architectures 477

8 Chip Design 491

8.1 Introduction 491

8.2 Hierarchical Chip Design 503

8.3 Application-Speci_c Integrated Circuit Designs (ASICs), Custom Designs, and Semi-Custom Designs 512

8.4 Catalog of Back-End-of-Line (BEOL) Interconnection Implementations 526

9 Structures, Yield, and Variation in Semiconductor Manufacturing 543

9.1 Introduction 544

9.2 Transistor Structures 546

9.3 Interconnection Structures 553

9.4 Yield 571

9.5 Variation in Electrical Properties of Transistors 590